1. Technical Field
The present invention pertains to testing of semi-conductor wafers. In particular, the present invention pertains to selective access and configuration of individual chips of a semi-conductor wafer for wafer level testing.
2. Discussion of Related Art
Generally, semi-conductor wafers include a plurality of chips or circuits (e.g., a Dynamic Random Access Memory (DRAM) wafer may include five-hundred chips) that are tested prior to packaging and implementation. Each chip may temporarily adjust internal voltages and other settings by altering values in corresponding chip registers. Once the register settings are optimized, the values may be permanently stored in the registers by disabling corresponding metal fuses that enable adjustment of the register values.
During wafer level testing (e.g., prior to permanent storage of the register settings), the internal voltages or other settings of the chips may be adjusted and parametric or functional tests may be performed. Each chip typically receives the same register settings since the chips are tested in a parallel fashion. The parameter adjustment allows for testing of the chip with the same conditions encountered after the permanent storage. However, various characteristics (e.g., measured internal voltages, etc.) of the chips may vary due to process variation. For example, one chip may have an internal voltage of 1.0 V while another chip may have an internal voltage of 1.1V.
In order to minimize the variation, each chip should have an individual adjustment or setting. However, since the chips are tested in a parallel fashion as described above, each chip receives the same register settings, thereby preventing individual adjustment of each chip to mitigate the variation.
The related art has provided a technique to enable the individual wafer chips to receive different register settings in an attempt to overcome this problem. Initially, the wafer level test may utilize various test mode commands that are recognized by the chips to initiate and control testing of the chips. These commands are typically issued from a wafer testing machine. For example, a mode register set (MRS) command may be employed to enable a value to be stored in a chip register. Further, an activate command may be utilized to place a chip in an active state (e.g., non-test mode state), where the chip ignores mode register set and other test mode commands (e.g., the chip registers may not be adjusted while the chip is in the active state).
In order to adjust settings of individual chips, each chip is initially powered down. A first chip is selected and power is enabled to that chip. A mode register set command is issued for the first chip with corresponding register settings. Since the remaining chips are powered down or disabled, the selected chip is configured with the desired settings. The first chip is subsequently issued an activate command to enter an active state. This enables the configured chip to ignore subsequent mode register set commands configuring other chips as described above. The remaining chips are configured in substantially the same manner described above, where a selected chip receives the desired settings via a mode register set command. The other chips that are either in an active state (e.g., previously configured) or are disabled due to lack of power (e.g., not yet configured) ignore the mode register set commands for the selected chip, thereby enabling configuration of a single chip at one time. Once each of the chips have received desired settings, parametric measurement or function tests may be performed on the chips in a parallel fashion to evaluate the settings.
The related art suffers from several disadvantages. In particular, the related art technique depends upon the powering on and off of a chip. In other words, the chip is required to power off and power on prior to setting of each parameter for performing a test, thereby increasing the time and complexity of performing wafer tests.
In addition, chips are typically tested in a parallel fashion to reduce testing time and enhance throughput. Although addresses and commands may be shared by all chips in this type of testing mode, test information (e.g., pass/fail, etc.) is unique to each chip, thereby requiring each chip to have a dedicated Input/Output (I/O) line. Since a wafer testing machine has a fixed quantity of available contacts to engage chip I/O lines for testing, the dedicated I/O line for each chip increases usage of available testing machine contacts and limits the quantity of chips that may be tested in parallel.